1. Field of the Invention
The present invention relates to techniques for communicating signals between semiconductor dies. More specifically, the present invention relates to a method and an apparatus for determining misalignment between semiconductor dies by comparing coupling capacitances in different capacitive connections between the semiconductor dies.
2. Related Art
Advances in semiconductor technology presently make it possible to integrate large-scale systems, which can include tens of millions of transistors, into a single semiconductor chip. Integrating such large-scale systems onto a single semiconductor chip increases the speed at which such systems can operate, because signals between system components do not have to cross chip boundaries, and are not subject to lengthy chip-to-chip propagation delays. Moreover, integrating large-scale systems onto a single semiconductor chip significantly reduces production costs, because fewer semiconductor chips are required to perform a given computational task.
Unfortunately, these advances in semiconductor technology have not been matched by corresponding advances in inter-chip communication technology. Semiconductor chips are typically integrated onto a printed circuit board that contains multiple layers of signal lines for inter-chip communication. However, signal lines on a semiconductor chip are about 100 times more densely packed than signal lines on a printed circuit board. Consequently, only a tiny fraction of the signal lines on a semiconductor chip can be routed across the printed circuit board to other chips. This problem has created a bottleneck that continues to grow as semiconductor integration densities continue to increase.
Researchers have begun to investigate alternative techniques for communicating between semiconductor chips. One promising technique involves integrating arrays of capacitive transmitters and receivers onto semiconductor chips to facilitate inter-chip communication. If a first chip is situated face-to-face with a second chip so that transmitter pads on the first chip are capacitively coupled with receiver pads on the second chip, the first chip can directly transmit signals to the second chip without having to route the signals through intervening signal lines within a printed circuit board.
Capacitive coupling requires precise alignment between the transmitter pads and the receiver pads, both in a plane defined by the pads and in a direction perpendicular to the plane. Misalignment between the transmitter pads and the receiver pads may cause each receiving pad to span two transmitting pads, thereby destroying a received signal. In theory, for communication to be possible chips must be aligned so that misalignment is less than half of a pitch between the pads. In practice, the alignment requirements may be more stringent. In addition, reducing misalignment can improve communication performance between the chips and reduce power consumption.
Unfortunately, it can be very challenging to align chips properly. Existing approaches include mechanical mounting structures that facilitate self-alignment and/or self-adjustment of pad positions. However, because of thermal expansion and mechanical vibrations, as well as manufacturing and assembly perturbations, even if the systems are assembled very carefully chips often still have some residual misalignment. Other techniques such as electronic steering, in which data signals are routed to particular pads in an array of pads, may also be used to further reduce the effects of misalignment. However, in order for the above-described techniques to work it is first necessary to precisely measure the alignment between chips.
One existing alignment measurement technique assigns a charge to conducting pads on one chip, and detects a pattern of charges that are induced in the pads on a facing chip. A variation on this technique provides an array of conductive pads on the first chip and an array of conductive pads on the second chip with a different spacing or pitch than the conductive pads on the first chip. When the conductive pads on the first chip overlap with the conductive pads on the second chip, a Vernier structure is created, which allows the alignment between the chips to be determined.
Another existing measurement technique determines chip separation. In this technique, a periodic signal is applied to conducting pads on one chip, and the charges induced on the pads on a facing chip are rectified. The coupling capacitance may be calculated from the amplitude of the resulting rectified current, and the chip separation may be determined from the coupling capacitance.
However, these existing approaches have limitations. These techniques are complex and measurements performed using these techniques are often slow. Moreover, results may be inaccurate, especially for small misalignments, since these techniques rely on being able to detect very small changes in capacitance for each pad. Unfortunately, because of noise and other instrument limitations, such as transistor leakage, it is often not possible to accurately detect such small changes in capacitance using these techniques.
Hence what is needed is a method and an apparatus to determine misalignment and facilitate capacitive inter-chip communication without the problems listed above.